US 11,990,996 B2
High speed interconnect symbol stream forward error-correction
Nausheen Ansari, Folsom, CA (US); Ziv Kabiry, Haifa (IL); and Gal Yedidia, Haifa (IL)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Oct. 17, 2022, as Appl. No. 17/967,125.
Application 17/967,125 is a continuation of application No. 17/353,000, filed on Jun. 21, 2021, granted, now 11,522,640.
Application 17/353,000 is a continuation of application No. 16/524,613, filed on Jul. 29, 2019, granted, now 11,044,045, issued on Jun. 22, 2021.
Application 16/524,613 is a continuation of application No. 15/089,251, filed on Apr. 1, 2016, granted, now 10,367,605, issued on Jul. 30, 2019.
Claims priority of provisional application 62/188,109, filed on Jul. 2, 2015.
Prior Publication US 2023/0103769 A1, Apr. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 1/00 (2006.01); H03M 5/00 (2006.01); H03M 5/14 (2006.01); H03M 13/00 (2006.01); H03M 13/15 (2006.01); H03M 13/29 (2006.01); H03M 13/31 (2006.01)
CPC H04L 1/0057 (2013.01) [H03M 5/145 (2013.01); H03M 13/1515 (2013.01); H03M 13/2906 (2013.01); H03M 13/31 (2013.01); H04L 1/0041 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for a transmitter, comprising physical (PHY) layer circuitry arranged to:
encode link layer symbols based on an 8b10b encoding scheme;
interleave symbols corresponding to a symbol stream to form a plurality of interleaved forward error correction (FEC) blocks;
generate a plurality of Reed Solomon (RS) parity symbols for the plurality of interleaved FEC blocks;
generate a FEC symbol stream from the plurality of FEC blocks and the plurality of RS parity symbols; and
send the FEC symbol stream to a receiver device.