CPC H03M 1/462 (2013.01) [H03M 1/008 (2013.01); H03M 1/0604 (2013.01); H03M 1/0626 (2013.01); H03M 1/122 (2013.01)] | 20 Claims |
1. A circuit, comprising:
an incremental analog to digital converter, comprising:
a loop filter that filters an analog input signal in response to receiving a reset signal, resulting in a filtered analog input signal; and
a successive approximation register (SAR) quantizer, coupled with the filtered analog input signal, that converts the filtered analog input signal to a first intermediate digitized output based on a first reference voltage, wherein the SAR quantizer comprises a feedback loop that shapes quantization noise generated by the SAR quantizer as a result of converting the filtered analog input signal, and wherein the first intermediate digitized output has a first resolution;
a digital to analog converter, coupled with the first intermediate digitized output, that converts the first intermediate digitized output to a converted analog signal;
a differential amplifier that subtracts the converted analog signal from the analog input signal, resulting in a residual analog input signal, wherein the SAR quantizer converts the residual analog input signal to a second intermediate digitized output based on a second reference voltage that is lower than the first reference voltage; and
a digital filter, coupled with the first intermediate digitized output, that generates a digitized output signal by digitally filtering the first intermediate digitized output, wherein the digitized output signal has a second resolution that is greater than the first resolution.
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