US 11,990,914 B2
Phase lock loop reference loss detection
Shailesh Ganapat Ghotgalkar, Bangalore (IN); Wei Fu, Plano, TX (US); and Venkatseema Das, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Dec. 14, 2021, as Appl. No. 17/550,123.
Application 17/550,123 is a continuation of application No. 16/940,880, filed on Jul. 28, 2020, granted, now 11,239,847.
Application 16/940,880 is a continuation of application No. 16/167,440, filed on Oct. 22, 2018, granted, now 10,727,841, issued on Jul. 28, 2020.
Prior Publication US 2022/0103181 A1, Mar. 31, 2022
Int. Cl. H03L 7/087 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/087 (2013.01) [H03L 7/099 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic circuit comprising:
a first input configured to receive a first signal synchronized to a first clock signal;
a second input configured to receive a second signal synchronized to a second clock signal;
a comparator circuit coupled to the first input and the second input, the comparator circuit configured to perform a comparison of the first signal and the second signal; and
an output configured to output a fault signal based on the comparison, wherein the first signal is an output from a clock divider or the second signal is an output from a code generator configured to generate a code in response to an input reference signal.