US 11,990,912 B2
Data transmission using delayed timing signals
Frederick A. Ware, Los Altos Hills, CA (US); Ely Tsern, Los Altos, CA (US); Brian Leibowitz, San Francisco, CA (US); and Jared Zerbe, Woodside, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Aug. 8, 2022, as Appl. No. 17/883,345.
Application 17/883,345 is a continuation of application No. 16/880,694, filed on May 21, 2020, granted, now 11,451,218.
Application 16/880,694 is a continuation of application No. 15/824,892, filed on Nov. 28, 2017, granted, now 10,700,671, issued on Jun. 30, 2020.
Application 15/824,892 is a continuation of application No. 14/351,955, granted, now 9,843,315, issued on Dec. 12, 2017, previously published as PCT/US2012/062301, filed on Oct. 26, 2012.
Claims priority of provisional application 61/711,660, filed on Oct. 9, 2012.
Claims priority of provisional application 61/554,492, filed on Nov. 1, 2011.
Prior Publication US 2023/0073567 A1, Mar. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 5/13 (2014.01); G06F 13/00 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G11C 7/04 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/02 (2006.01)
CPC H03K 5/13 (2013.01) [G06F 13/1689 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 7/22 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G06F 13/00 (2013.01); G06F 13/4243 (2013.01); G11C 7/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller to control an operation of a memory device having a plurality of memory cells, the memory controller comprising:
a first transmitter circuit to transmit data to the memory device, the data for storage in the plurality of memory cells;
a second transmitter circuit to transmit a first timing signal to the memory device, the first timing signal to time reception of the data at the memory device;
a receiver circuit to receive, from the memory device, a signal indicative of a phase comparison between a phase of the first timing signal and a phase of the data, the signal indicative of the phase comparison having a first value in response to a transition in the data leading an edge of the first timing signal, and the signal indicative of the phase comparison having a second value in response to the transition in the data lagging the edge of the first timing signal; and
a circuit to adjust, a transmit phase of data transmission by the first transmitter circuit, based on the signal indicative of the phase comparison.