US 11,990,907 B2
Closed loop oscillator
Nandakishore Raimar, Bangalore (IN); Brajveer Singh, Kammnahalli (IN); and Iulian Gradinariu, Colorado Springs, CO (US)
Assigned to Cypress Semiconductor Corporation, San Jose, CA (US)
Filed by Cypress Semiconductor Corporation, San Jose, CA (US)
Filed on Sep. 27, 2022, as Appl. No. 17/954,126.
Prior Publication US 2024/0106422 A1, Mar. 28, 2024
Int. Cl. H03K 3/0231 (2006.01); H03B 5/04 (2006.01); H03B 5/24 (2006.01); H03K 3/03 (2006.01); H03L 7/099 (2006.01)
CPC H03K 3/0231 (2013.01) [H03B 5/04 (2013.01); H03B 5/24 (2013.01); H03K 3/0315 (2013.01); H03L 7/0992 (2013.01); H03L 7/0995 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An oscillator, comprising:
a voltage controlled oscillator configured to generate an output clock based on a drive signal;
a frequency to voltage converter having a time constant and configured to generate a feedback voltage having a decay cycle based on the time constant and a frequency based on a frequency of the output clock, wherein the frequency to voltage converter comprises:
a first capacitor connected to a supply voltage,
a first resistor connected to the first capacitor at a first node and connected to a reference potential, and
a first transistor connected to the supply voltage and the first node, wherein:
an integrator is connected to the first node to receive the feedback voltage
the integrator configured to generate the drive signal based on an integration of the feedback voltage and a reference voltage; and
a frequency divider configured to receive the output clock and generate a feedback clock having a frequency corresponding to a frequency of the output clock divided by an integer, wherein the feedback clock is connected to a gate of the first transistor.