US 11,990,901 B2
Semiconductor circuit and support device for logic circuit design
Ko Yoshikawa, Sendai (JP); Yitao Ma, Sendai (JP); Tetsuo Endoh, Sendai (JP); Osamu Nomura, Sendai (JP); and Li Tao, Sendai (JP)
Assigned to TOHOKU UNIVERSITY, Sendai (JP)
Filed by TOHOKU UNIVERSITY, Sendai (JP)
Filed on Sep. 8, 2022, as Appl. No. 17/940,600.
Claims priority of application No. 2021-148212 (JP), filed on Sep. 10, 2021.
Prior Publication US 2023/0084986 A1, Mar. 16, 2023
Int. Cl. H03K 3/01 (2006.01); G06F 1/04 (2006.01); G06F 1/08 (2006.01); G06F 30/396 (2020.01); H03K 3/037 (2006.01); H03K 19/00 (2006.01); H03K 19/20 (2006.01)
CPC H03K 19/0016 (2013.01) [G06F 1/04 (2013.01); G06F 1/08 (2013.01); G06F 30/396 (2020.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor circuit device, comprising:
a first clock gating circuit configured to output a first gated clock signal generated from a clock signal, in response to a first enable signal that enables or disables the clock signal;
a non-volatile first flip-flop configured to operate in response to a clock pulse of the first gated clock signal;
an acquisition circuit, configured to acquire data inputted from the first flip-flop, directly or via a combinational circuit, according to a second enable signal that enables or disables the acquisition of the data from the first flip-flop; and
a power gating circuit including a power switch that is provided on a power source line through which electric power is supplied to the first flip-flop, the power gating circuit receiving the first enable signal and the second enable signal as power source control signals, and supplying the electric power to the first flip-flop by turning ON the power switch when the first enable signal has a logical value that enables the clock signal or when the second enable signal has a logical value that enables the acquisition of the data in the acquisition circuit.