US 11,990,875 B2
Bias circuit and power amplifier circuit
Christian Elgaard, Lund (SE); and Henrik Sjöland, Lund (SE)
Assigned to Telefonaktiebolaget LM Ericsson (Publ), Stockholm (SE)
Appl. No. 17/421,289
Filed by Telefonaktiebolaget LM Ericsson (publ), Stockholm (SE)
PCT Filed Aug. 29, 2019, PCT No. PCT/EP2019/073046
§ 371(c)(1), (2) Date Jul. 7, 2021,
PCT Pub. No. WO2020/143934, PCT Pub. Date Jul. 16, 2020.
Claims priority of provisional application 62/790,767, filed on Jan. 10, 2019.
Prior Publication US 2022/0123697 A1, Apr. 21, 2022
Int. Cl. H03F 3/24 (2006.01)
CPC H03F 3/245 (2013.01) [H03F 2200/451 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A bias circuit for a power amplifier, PA, the bias circuit comprising:
a first transistor having its drain terminal and its gate terminal connected to a first circuit node and its source terminal connected to a first supply terminal;
a first current source connected to the first circuit node;
a first resistor connected between the first circuit node and a second circuit node;
a second transistor configured to receive a first component of a differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal;
a third transistor configured to receive a second component of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal;
a fourth transistor having its gate terminal connected to a third circuit node, its drain terminal connected to the first circuit node, and its source terminal connected to the first supply terminal;
the gate terminals of the second transistor and the third transistor being configured to be biased by a first voltage; and
the bias circuit being configured to generate a bias voltage for the PA at the second circuit node.