US 11,990,747 B2
Electrostatic protection circuit and semiconductor integrated circuit
Hiroshi Uemura, Osaka (JP); and Keiji Tanaka, Osaka (JP)
Assigned to SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka (JP)
Filed by SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka (JP)
Filed on Nov. 17, 2021, as Appl. No. 17/528,706.
Claims priority of application No. 2020-192372 (JP), filed on Nov. 19, 2020.
Prior Publication US 2022/0158447 A1, May 19, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H02H 9/04 (2006.01); H01L 27/02 (2006.01); H02H 1/00 (2006.01); H03K 17/082 (2006.01)
CPC H02H 9/046 (2013.01) [H02H 1/0007 (2013.01); H03K 17/0826 (2013.01); H01L 27/0248 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An electrostatic protection circuit comprising:
a first output terminal and a second output terminal;
a common node having an intermediate voltage;
a first diode connected between the first output terminal and the common node;
a second diode connected between the second output terminal and the common node;
an intermediate voltage circuit including a first dividing resistor and a second dividing resistor, the first dividing resistor being connected between the first output terminal and the common node in parallel with the first diode, the second dividing resistor being connected between the second output terminal and the common node in parallel with the second diode; and
a clamp circuit connected between the common node and a ground line, the clamp circuit being configured to electrically connect the common node to the ground line in accordance with the intermediate voltage.