US 11,990,709 B2
High speed differential pinout arrangement including a power pin
Raul Enriquez Shibayama, Zapopan (MX); Carlos Alberto Lizalde Moreno, Guadalajara (MX); Gaudencio Hernandez Sosa, Guadalajara (MX); and Kai Xiao, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 16, 2020, as Appl. No. 16/902,832.
Prior Publication US 2021/0391671 A1, Dec. 16, 2021
Int. Cl. H01R 13/00 (2006.01); H01R 12/71 (2011.01); H01R 13/6469 (2011.01); H01R 13/6471 (2011.01); H05K 7/14 (2006.01)
CPC H01R 13/6469 (2013.01) [H01R 12/718 (2013.01); H01R 13/6471 (2013.01); H05K 7/1452 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic device having a hexagonal node configuration, comprising:
a differential signal node pair;
a miscellaneous node;
a power node; and
a plurality of ground nodes; and
wherein the differential signal node pair, the miscellaneous node, the power node, and the plurality of ground nodes are arranged in a hexagonal parallelogon pattern, wherein the differential signal node pair includes a first differential signal node adjacent to a second differential signal node, wherein the power node is adjacent and symmetric to the differential signal node pair, and wherein the miscellaneous node is adjacent and symmetric to the differential signal node pair.