US 11,990,552 B2
Semiconductor devices
Ryong Ha, Seoul (KR); Seok Hoon Kim, Suwon-si (KR); Jung Taek Kim, Yongin-si (KR); Pan Kwi Park, Incheon (KR); Moon Seung Yang, Hwaseong-si (KR); and Seo Jin Jeong, Incheon (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 23, 2021, as Appl. No. 17/533,719.
Claims priority of application No. 10-2020-0170073 (KR), filed on Dec. 8, 2020.
Prior Publication US 2022/0181500 A1, Jun. 9, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/78618 (2013.01) [H01L 29/6653 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01); H01L 29/42392 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an active pattern comprising a lower pattern and a sheet pattern, wherein the sheet pattern is spaced apart from the lower pattern in a first direction;
a gate structure on the lower pattern, wherein the gate structure comprises a gate electrode that surrounds the sheet pattern, and wherein the gate electrode extends in a second direction that is perpendicular to the first direction; and
a source/drain pattern on the lower pattern and in contact with the sheet pattern,
wherein a contact surface between the sheet pattern and the source/drain pattern has a first width in the second direction,
wherein the sheet pattern has a second width in the second direction that is greater than the first width,
wherein the sheet pattern comprises an epi-trench at one end of the sheet pattern that penetrates the sheet pattern in a third direction perpendicular to the first direction and the second direction, and
wherein a part of the source/drain pattern is within the epi-trench.