US 11,990,550 B2
Semiconductor structure with source/drain multi-layer structure and method for forming the same
Chun-Chieh Wang, Kaohsiung (TW); Yu-Ting Lin, Tainan (TW); Yueh-Ching Pai, Taichung (TW); Shih-Chieh Chang, Taipei (TW); and Huai-Tei Yang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 9, 2022, as Appl. No. 18/063,711.
Application 18/063,711 is a continuation of application No. 17/155,467, filed on Jan. 22, 2021, granted, now 11,527,655.
Application 17/155,467 is a continuation of application No. 16/654,175, filed on Oct. 16, 2019, granted, now 10,937,910, issued on Mar. 2, 2021.
Application 16/654,175 is a continuation of application No. 16/043,371, filed on Jul. 24, 2018, granted, now 10,468,530, issued on Nov. 5, 2019.
Claims priority of provisional application 62/586,272, filed on Nov. 15, 2017.
Prior Publication US 2023/0109135 A1, Apr. 6, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/32 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7856 (2013.01) [H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/3065 (2013.01); H01L 21/3105 (2013.01); H01L 21/31116 (2013.01); H01L 21/32 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/66553 (2013.01); H01L 29/66795 (2013.01); H01L 29/66803 (2013.01); H01L 21/823814 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a gate structure formed over a fin structure, wherein the gate structure comprises a gate dielectric layer;
a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure;
a S/D silicide layer formed on the S/D epitaxial layer, wherein the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width; and
a dielectric spacer between the gate structure and the S/D silicide layer, wherein a top surface of the dielectric spacer is lower than a top surface of the gate structure, and an interface between the dielectric spacer and the S/D epitaxial layer is higher than a bottommost surface of the gate dielectric layer, wherein a topmost surface of the gate dielectric layer is higher than a top surface of the dielectric spacer.