US 11,990,548 B2
Transistor with low leakage currents and manufacturing method thereof
Chao-Chun Lu, Taipei (TW); and Weng-Dah Ken, Hsinchu (TW)
Assigned to Etron Technology, Inc., Hsinchu (TW); and Invention And Collaboration Laboratory Pte. Ltd., Singapore (SG)
Filed by Etron Technology, Inc., Hsinchu (TW)
Filed on May 27, 2020, as Appl. No. 16/885,210.
Claims priority of provisional application 62/853,175, filed on May 28, 2019.
Prior Publication US 2020/0381548 A1, Dec. 3, 2020
Int. Cl. H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 29/0847 (2013.01); H01L 29/41775 (2013.01); H01L 29/41791 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01)] 17 Claims
OG exemplary drawing
 
17. A transistor with low leakage currents, comprising:
a substrate;
a gate formed above a gate dielectric layer;
a spacer, wherein the spacer comprises at least two sublayers;
a pad dielectric layer formed under the spacer, wherein a bottom of each sublayer of the spacer completely contacts with the pad dielectric layer; and
a source region or a drain region, wherein the source region or the drain region is adjacent to the spacer;
wherein the gate dielectric layer has a bottom directly contacted with the substrate and has a curved corner contacted with the pad dielectric layer, and a maximum width between two most lateral edges of the curved corners of the gate dielectric layer is not greater than a width between two most lateral edges of sidewalls of the gate dielectric layer.