US 11,990,536 B2
Bipolar transistors with multilayer collectors
Johannes Josephus Theodorus Marinus Donkers, Valkenswaard (NL); Petrus Hubertus Cornelis Magnee, Malden (NL); and Ronald Willem Arnoud Werkman, Groesbeek (NL)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Dec. 31, 2021, as Appl. No. 17/646,716.
Prior Publication US 2023/0215937 A1, Jul. 6, 2023
Int. Cl. H01L 29/737 (2006.01); H01L 27/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/737 (2013.01) [H01L 27/0623 (2013.01); H01L 29/0821 (2013.01); H01L 29/66242 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method of manufacturing a heterojunction bipolar transistor, comprising:
forming a semiconductor collector region in a substrate by:
forming a lower collector layer within the substrate;
forming a barrier layer above the lower collector layer such that the barrier layer is configured to impede diffusion of dopants from the lower collector layer through the barrier layer during one or more subsequent manufacturing steps, wherein the barrier layer is located at peripheral sides of the semiconductor collector region, separate from a center of the semiconductor collector region; and
forming an upper collector layer above the barrier layer;
forming a trench isolation region in the substrate that electrically insulates the semiconductor collector region, wherein the barrier layer is adjacent to the trench isolation region;
selectively forming a heterogeneous base region on a portion of the semiconductor collector region by forming a heterogeneous stack of semiconductor layers; and
selectively forming an emitter region on a portion of the heterogeneous base region.