US 11,990,529 B2
Air gap in inner spacers and methods of fabricating the same in field-effect transistors
Chien Ning Yao, Hsinchu (TW); Bo-Feng Young, Taipei (TW); Sai-Hooi Yeong, Hsinchu County (TW); Kuan-Lun Cheng, Hsin-Chu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 14, 2022, as Appl. No. 18/055,286.
Application 18/055,286 is a continuation of application No. 17/107,374, filed on Nov. 30, 2020, granted, now 11,502,183.
Claims priority of provisional application 62/967,285, filed on Jan. 29, 2020.
Prior Publication US 2023/0080922 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/49 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/764 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/4991 (2013.01) [H01L 21/02603 (2013.01); H01L 21/28123 (2013.01); H01L 21/764 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a dummy gate stack over a fin;
forming an S/D recess in the fin;
depositing a first spacer layer within the S/D recess, wherein the depositing forms a plurality of air gaps in the first spacer layer, and wherein each of the plurality of air gaps is surrounded by the first spacer layer;
before forming an epitaxial source/drain (S/D) feature, removing portions of the first spacer layer adjacent the fin while maintaining the plurality of air gaps surrounded by the first spacer layer; and
forming the epitaxial S/D feature in the S/D recess and laterally adjacent to the first spacer layer having the plurality of air gaps.