CPC H01L 29/4966 (2013.01) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02)] | 16 Claims |
1. A memory array, comprising:
a plurality of wordlines each comprising:
a core comprising a first metal-containing material;
an intermediate region around the core, the intermediate region comprising a second metal containing material; and
an outer region comprising a third metal-containing material around the intermediate region, the first, second and third metal-containing materials each being compositionally different from one another, the second metal-containing material being in direct physical contact with the first metal-containing material and the third metal-containing material, wherein the second metal-containing material is an electrically insulative material having a thickness configured to enable a conductive gate in each wordline to retain conductive properties.
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