US 11,990,519 B2
And manufacture of power devices having increased cross over current
Siddarth Sundaresan, Dulles, VA (US); Ranbir Singh, Dulles, VA (US); and Jaehoon Park, Dulles, VA (US)
Assigned to GENESIC SEMICONDUCTOR INC., Dulles, VA (US)
Filed by GeneSiC Semiconductor Inc., Dulles, VA (US)
Filed on Apr. 12, 2021, as Appl. No. 17/227,936.
Application 17/227,936 is a division of application No. 16/945,781, filed on Jul. 31, 2020, granted, now 11,004,940.
Prior Publication US 2022/0037472 A1, Feb. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/16 (2006.01); H01L 27/02 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/1608 (2013.01) [H01L 27/0255 (2013.01); H01L 29/4933 (2013.01); H01L 29/7804 (2013.01); H01L 29/7813 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A device comprising a unit cell on a Silicon Carbide (SiC) substrate, the unit cell comprising:
a first conductivity type source region on the SiC substrate;
a second conductivity type well region that contains the first conductivity type source region;
and
a silicide layer interrupted by interlayer dielectric (ILD) regions on the SiC substrate,
wherein the device comprises a vertical Silicon Carbide double-implantation metal oxide semiconductor field-effect transistor (DMOSFET) comprising a drain terminal and a source terminal on the SiC substrate,
wherein the source terminal is located on a first side of the SiC substrate and the drain terminal is located on a second side of the SiC substrate,
wherein the source terminal is in contact with the silicide layer,
wherein a second conductivity type well contact region meanders within the second conductivity type well region to form a periodic contact region with the source terminal through the silicide layer, and
wherein the periodic contact region provides reduced contact area.