US 11,990,515 B2
Up-diffusion suppression in a power MOSFET
Prasad Venkatraman, Gilbert, AZ (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Dec. 8, 2022, as Appl. No. 18/063,086.
Application 18/063,086 is a division of application No. 16/948,806, filed on Oct. 1, 2020, granted, now 11,527,618.
Claims priority of provisional application 62/705,864, filed on Jul. 18, 2020.
Prior Publication US 2023/0106080 A1, Apr. 6, 2023
Int. Cl. H01L 29/10 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 29/167 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/1095 (2013.01) [H01L 21/2253 (2013.01); H01L 21/2652 (2013.01); H01L 29/167 (2013.01); H01L 29/407 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for preparing a substrate for fabricating a vertical MOSFET device, the method comprising:
forming a first epitaxial layer on a silicon wafer;
forming an ion-implanted capping layer in the first epitaxial layer; and
forming a device layer over the first epitaxial layer,
the silicon wafer being a phosphorus doped n+ silicon wafer, the first epitaxial layer being doped with phosphorus, the ion-implanted capping layer being an arsenic-implanted buried layer, and
wherein forming the device layer over the first epitaxial layer includes forming a source of the device in the device layer and forming a drain of the device in the silicon wafer.