US 11,990,513 B2
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
Cory Bomberger, Portland, OR (US); Anand Murthy, Portland, OR (US); Susmita Ghose, Hillsboro, OR (US); and Siddharth Chouksey, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 16, 2022, as Appl. No. 17/988,612.
Application 17/988,612 is a continuation of application No. 16/369,760, filed on Mar. 29, 2019, granted, now 11,532,706.
Prior Publication US 2023/0082276 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/167 (2006.01); H01L 29/32 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/027 (2006.01); H01L 21/66 (2006.01)
CPC H01L 29/0847 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02535 (2013.01); H01L 21/30604 (2013.01); H01L 29/0673 (2013.01); H01L 29/1037 (2013.01); H01L 29/165 (2013.01); H01L 29/167 (2013.01); H01L 29/32 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/0276 (2013.01); H01L 21/30625 (2013.01); H01L 22/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a semiconductor fin;
a nanowire above the semiconductor fin;
a gate stack over the semiconductor fin and around the nanowire, the gate stack having a first side and a second side, the second side opposite the first side;
a first boron-doped germanium tin epitaxial source or drain structure on the semiconductor fin and at a first end of the nanowire, and adjacent to the first side of the gate stack; and
a second boron-doped germanium tin epitaxial source or drain structure on the semiconductor fin and at a first end of the nanowire and adjacent to the second side of the gate stack.