US 11,990,510 B2
Semiconductor device and manufacturing method thereof
Cheng-Yi Peng, Taipei (TW); Ting Tsai, Hsinchu (TW); Chung-Wei Hung, Tainan (TW); Jung-Ting Chen, Zhubei (TW); Ying-Hua Lai, Taipei (TW); Song-Bor Lee, Zhubei (TW); and Bor-Zen Tien, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 26, 2021, as Appl. No. 17/385,031.
Application 17/385,031 is a continuation of application No. 16/596,534, filed on Oct. 8, 2019, granted, now 11,075,269, issued on Jul. 27, 2021.
Claims priority of provisional application 62/774,150, filed on Nov. 30, 2018.
Prior Publication US 2021/0359085 A1, Nov. 18, 2021
Int. Cl. H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 29/24 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0847 (2013.01) [H01L 29/24 (2013.01); H01L 21/02521 (2013.01); H01L 21/02529 (2013.01); H01L 21/0262 (2013.01); H01L 21/26513 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a fin structure extending along a first direction having a channel region protruding from an isolation insulating layer;
a gate structure extending in a second direction disposed over the channel region and including a gate dielectric layer, a gate electrode layer and a sidewall spacer,
wherein the second direction is perpendicular to the first direction; and
a source/drain region adjacent to the channel region, wherein:
the source/drain region includes a first layer, a second layer formed on the first layer and a third layer formed on the second layer,
the first layer includes As,
the second layer includes SiP,
the third layer includes SiAs,
a bottom of the second layer is located below an upper surface of the isolation insulating layer, and
the first layer extends below the sidewall spacer along the first direction as viewed along a third direction perpendicular to the first and second directions.