US 11,990,506 B2
Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same
Jiajia Wu, Wuhan (CN); Jingjing Geng, Wuhan (CN); Yang Zhou, Wuhan (CN); Zhen Guo, Wuhan (CN); Meng Xiao, Wuhan (CN); and Hui Zhang, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Oct. 29, 2020, as Appl. No. 17/084,346.
Application 17/084,346 is a continuation of application No. PCT/CN2020/113429, filed on Sep. 4, 2020.
Prior Publication US 2022/0077283 A1, Mar. 10, 2022
Int. Cl. H01L 29/06 (2006.01); G11C 8/14 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H01L 29/0649 (2013.01) [G11C 8/14 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack on the substrate comprising a plurality of interleaved conductive layers and dielectric layers, an outmost one of the conductive layers toward the substrate being a source select gate line (SSG);
a plurality of channel structures each extending vertically through the memory stack; and
one or more isolation structures each surrounding at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure,
wherein a first group of the plurality of channel structures is spaced apart from the SSG and a second group of the plurality of channel structures is in direct contact with the SSG.