US 11,990,504 B2
Capacitor with MIM
Yoshihide Komatsu, Yokohama (JP); Takeshi Igarashi, Yokohama (JP); and Hiroyuki Oguri, Yokohama (JP)
Assigned to SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC., Kanagawa (JP)
Filed by SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC., Kanagawa (JP)
Filed on Jul. 7, 2021, as Appl. No. 17/369,705.
Application 17/369,705 is a continuation of application No. 16/411,668, filed on May 14, 2019, granted, now 11,152,457.
Claims priority of application No. 2018-093539 (JP), filed on May 15, 2018.
Prior Publication US 2021/0335992 A1, Oct. 28, 2021
Int. Cl. H01L 23/52 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01)
CPC H01L 28/75 (2013.01) [H01L 23/5223 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A capacitor having an MIM, comprising:
a lower electrode;
an upper electrode; and
dielectric layers laminated on an upper surface of the lower electrode from the lower electrode to the upper electrode to form a dielectric for the capacitor;
wherein the dielectric layers include a first dielectric layer having a first thickness on an upper surface of the lower electrode, and a second dielectric layer having a second thickness on an upper surface of the first dielectric layer and being in contact with the upper electrode,
wherein, in plan view of the capacitor, the dielectric has a first defect portion and a second defect portion at different locations,
wherein the first defect portion is a depression at the upper surface of the first dielectric layer and does not go through the first dielectric layer to the lower electrode, and
wherein the second defect portion is a depression at the upper surface of the second dielectric layer and does not go through the second dielectric layer to the first dielectric layer.