US 11,990,483 B2
Array substrate and manufacturing method thereof
Ziran Li, Guangdong (CN)
Assigned to Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen (CN)
Appl. No. 17/438,956
Filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Guangdong (CN)
PCT Filed Aug. 6, 2021, PCT No. PCT/CN2021/111115
§ 371(c)(1), (2) Date Sep. 14, 2021,
PCT Pub. No. WO2023/004869, PCT Pub. Date Feb. 2, 2023.
Claims priority of application No. 202110862459.2 (CN), filed on Jul. 29, 2021.
Prior Publication US 2024/0030239 A1, Jan. 25, 2024
Int. Cl. H01L 27/12 (2006.01)
CPC H01L 27/1248 (2013.01) [H01L 27/1259 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
an underlay;
an active layer disposed on the underlay;
a gate electrode insulation layer, wherein the gate electrode insulation layer is disposed on the active layer and covers the active layer, the gate electrode insulation layer comprises a first through hole set and a second through hole set disposed oppositely; wherein the first through hole set comprises a first through hole and second through holes, the second through holes are defined in a side of the first through hole set near the second through hole set, the second through hole set comprises third through holes and a fourth through hole, the third through holes are defined in a side of the second through hole set near the first through hole set, and the second through holes and the third through holes each include a plurality of holes; and
a metal layer disposed on the gate electrode insulation layer, wherein the metal layer comprises a source electrode, a drain electrode, and a gate electrode, the drain electrode is connected to the active layer through the first through hole, and the source electrode is connected to the active layer through the fourth through hole.