US 11,990,477 B2
Hybrid fin field-effect transistor cell structures and related methods
Wei-An Lai, Taichung (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Jiann-Tyng Tzeng, Hsin Chu (TW); Wei-Cheng Lin, Taichung (TW); Lipen Yuan, Hsinchu County (TW); and Yan-Hao Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Sep. 24, 2020, as Appl. No. 17/030,573.
Application 17/030,573 is a division of application No. 16/102,803, filed on Aug. 14, 2018, granted, now 10,797,078.
Prior Publication US 2021/0005634 A1, Jan. 7, 2021
Int. Cl. H01L 27/118 (2006.01); H01L 27/02 (2006.01); H01L 27/08 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/1211 (2013.01) [H01L 27/0207 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a circuit cell, comprising:
accessing a logic design for implementing a function of the circuit cell, the logic design including a plurality of logic components;
accessing a plurality of circuit structures for implementing one or more of the logic components, the plurality of circuit structures including,
a first circuit structure comprising a first circuit component that includes fin field-effect transistors (finFETs) formed in a first fin portion of the circuit cell, the first fin portion including a plurality of first fin structures arranged in first rows, and
a second circuit structure comprising a second circuit component that includes finFETs formed in a second fin portion of the circuit cell, the second fin portion of the circuit including a plurality of second fin structures arranged in a plurality of second rows, wherein each of the second rows, in the second fin portion, contain a lesser number of fin structures than each of the first rows, in the first fin portion of the circuit cell;
generating a plurality of circuit designs that use different combinations of the plurality of circuit structures that implement the function;
filtering the generated circuit designs that do not meet a first circuit criterion; and
selecting a remaining circuit design that has an optimum value for a second circuit criterion.