US 11,990,475 B2
Semiconductor device
Ahreum Kim, Hwaseong-si (KR); Sunghoon Kim, Seongnam-si (KR); and Daeseok Byeon, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 29, 2021, as Appl. No. 17/536,413.
Claims priority of application No. 10-2020-0164392 (KR), filed on Nov. 30, 2020; and application No. 10-2021-0049678 (KR), filed on Apr. 16, 2021.
Prior Publication US 2022/0173100 A1, Jun. 2, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 25/065 (2023.01)
CPC H01L 27/0922 (2013.01) [H01L 21/823814 (2013.01); H01L 21/823892 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 27/0925 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06524 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
an N-well area formed in the substrate;
a first P-channel metal oxide semiconductor (PMOS) transistor having active regions formed in the N-well area; and
a first N-channel metal oxide semiconductor (NMOS) transistor having active regions formed in the substrate,
wherein the first NMOS transistor includes a first N-type active region overlapping each of the substrate and the N-well area, when viewed from above a plane parallel to a top surface of the substrate, and
wherein a first portion of the first N-type active region overlaps the N-well area from above the plane and is a well guard-ring of the N-well area.