US 11,990,474 B2
Method of making a semiconductor device
Shu Fang Fu, Hsinchu (TW); Chi-Feng Huang, Hsinchu (TW); Chia-Chung Chen, Hsinchu (TW); Victor Chiang Liang, Hsinchu (TW); and Fu-Huan Tsai, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 9, 2023, as Appl. No. 18/151,990.
Application 18/151,990 is a division of application No. 16/938,528, filed on Jul. 24, 2020, granted, now 11,552,076.
Application 16/586,273 is a division of application No. 15/255,370, filed on Sep. 2, 2016, granted, now 10,431,582, issued on Oct. 1, 2019.
Application 16/938,528 is a continuation of application No. 16/586,273, filed on Sep. 27, 2019, granted, now 10,741,553, issued on Aug. 11, 2020.
Claims priority of provisional application 62/343,735, filed on May 31, 2016.
Prior Publication US 2023/0163125 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/088 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H03K 3/03 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01); H01L 29/1041 (2013.01); H01L 29/7835 (2013.01); H01L 29/785 (2013.01); H01L 21/823814 (2013.01); H03K 3/0315 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, the method comprising:
forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip;
forming a first source/drain feature between the gate structure and the first edge structure;
forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature; and
implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.