US 11,990,472 B2
Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates
Leonard P. Guler, Hillsboro, OR (US); Michael K. Harper, Hillsboro, OR (US); William Hsu, Hillsboro, OR (US); Biswajeet Guha, Hillsboro, OR (US); Tahir Ghani, Portland, OR (US); Niels Zussblatt, Hillsboro, OR (US); Jeffrey Miles Tan, Hillsboro, OR (US); Benjamin Kriegel, Portland, OR (US); Mohit K. Haran, Hillsboro, OR (US); Reken Patel, Portland, OR (US); Oleg Golonzka, Beaverton, OR (US); and Mohammad Hasan, Aloha, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 23, 2020, as Appl. No. 17/030,212.
Prior Publication US 2022/0093592 A1, Mar. 24, 2022
Int. Cl. H01L 27/088 (2006.01); G11C 5/06 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [G11C 5/06 (2013.01); H01L 27/0688 (2013.01); H01L 29/0669 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a second gate stack over the second vertical arrangement of horizontal nanowires, an end of the second gate stack spaced apart from an end of the first gate stack by a gap; and
a dielectric structure comprising a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.