US 11,990,467 B2
Low capacitance bidirectional transient voltage suppressor
Shekar Mallikarjunaswamy, San Jose, CA (US); and Ning Shi, San Jose, CA (US)
Assigned to Alpha and Omega Semiconductor (Cayman) Ltd., Grand Cayman (KY)
Filed by Alpha and Omega Semiconductor (Cayman) Ltd., Grand Cayman (KY)
Filed on Sep. 14, 2022, as Appl. No. 17/931,902.
Application 17/931,902 is a continuation of application No. 17/147,808, filed on Jan. 13, 2021, granted, now 11,462,532.
Application 17/147,808 is a continuation of application No. 16/447,704, filed on Jun. 20, 2019, granted, now 10,937,780, issued on Mar. 2, 2021.
Application 16/447,704 is a continuation of application No. 16/045,570, filed on Jul. 25, 2018, granted, now 10,373,947, issued on Aug. 6, 2019.
Application 16/045,570 is a continuation of application No. 15/605,662, filed on May 25, 2017, granted, now 10,062,682, issued on Aug. 28, 2018.
Prior Publication US 2023/0050292 A1, Feb. 16, 2023
Int. Cl. H01L 27/02 (2006.01); H01L 23/535 (2006.01); H01L 29/06 (2006.01); H01L 29/861 (2006.01); H01L 29/866 (2006.01); H01L 29/87 (2006.01)
CPC H01L 27/0262 (2013.01) [H01L 23/535 (2013.01); H01L 27/0255 (2013.01); H01L 29/0649 (2013.01); H01L 29/8611 (2013.01); H01L 29/866 (2013.01); H01L 29/87 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A bidirectional circuit transient voltage suppressing (TVS) protection circuit, comprising:
a first high-side diode having an anode coupled to a first protected node and a cathode coupled to a first node;
a first low-side diode having a cathode coupled to the first protected node and an anode coupled to a second node;
a second high-side diode having an anode coupled to a second protected node and a cathode coupled to the first node;
a second low-side diode having a cathode coupled to the second protected node and an anode coupled to the second node;
a clamp circuit comprising a MOS transistor integrated with a silicon controlled rectifier (SCR), the SCR having an anode coupled to the first node, a cathode coupled to the second node, and a gate terminal, and the MOS transistor having a first current terminal coupled to the anode of the SCR through a first variable resistor, and a second current terminal coupled to the second node, wherein the gate terminal of the SCR is coupled to the second node through a second variable resistor; and
a trigger circuit comprising a third resistor and a first capacitor connected in series between the first node and the second node, a third node between the third resistor and the first capacitor being coupled to a gate terminal of the MOS transistor and the gate terminal of the SCR,
wherein in response to a voltage applied to one of the protected nodes exceeding a first voltage level, the trigger circuit drives the MOS transistor to cause a current flow at the SCR to trigger an SCR action and the SCR clamps the voltage at the respective protected node at a clamping voltage.