US 11,990,464 B2
Semiconductor integrated circuit device including opposite facing I/O cells in 2×2 columns
Toru Matsui, Yokohama (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by SOCIONEXT INC., Kanagawa (JP)
Filed on Mar. 17, 2021, as Appl. No. 17/204,797.
Application 17/204,797 is a continuation of application No. PCT/JP2018/036192, filed on Sep. 28, 2018.
Prior Publication US 2021/0202468 A1, Jul. 1, 2021
Int. Cl. H01L 27/02 (2006.01); H01L 27/11 (2006.01); H01L 27/118 (2006.01)
CPC H01L 27/0207 (2013.01) [H01L 27/11898 (2013.01); H01L 2224/0613 (2013.01); H01L 2224/06134 (2013.01); H01L 2224/0616 (2013.01); H01L 2224/06163 (2013.01); H01L 2224/06177 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device comprising:
a chip;
a core region on the chip; and
an IO region provided between the core region and a periphery of the chip on the chip, wherein
the IO region includes 2×N IO cell columns, where N is an integer of two or more, including a plurality of IO cells aligned in a first direction that is along the periphery of the chip, the IO cell columns being aligned in a second direction perpendicular to the first direction,
each of the IO cells includes a lower power supply voltage region and a higher power supply voltage region which are separately provided in the second direction,
the IO cell columns include a first IO cell column group including a first IO cell column in a position closest to the periphery of the chip with the lower power supply voltage region facing the core region, and a second IO cell column group including a second IO cell column in a position closest to the core region with the lower power supply voltage region facing the core region, and
at least one of the first IO cell column group or the second IO cell column group includes two or more IO cell columns, the two or more IO cell columns being aligned in the second direction such that the lower power supply voltage regions face each other or the higher power supply voltage regions face each other.