CPC H01L 25/18 (2013.01) [H01L 21/28194 (2013.01); H01L 21/324 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 27/0266 (2013.01); H01L 27/0886 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 2225/06541 (2013.01)] | 20 Claims |
1. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon layer;
a plurality of first transistors each comprising a single-crystal channel;
a first metal layer disposed over said plurality of first transistors;
a second metal layer disposed over said first metal layer;
a third metal layer disposed over said second metal layer;
a second level comprising a plurality of second transistors, said second level is disposed over said third metal layer;
a third level comprising a plurality of third transistors, said third level is disposed over said second level;
a fourth metal layer disposed over said third level;
a fifth metal layer disposed over said fourth metal layer;
a via disposed through said second level,
wherein at least one of said plurality of second transistors comprises a metal gate,
wherein processing of said second transistors comprises use of Atomic Layer Deposition (“ALD”),
wherein an average thickness of said fifth metal layer is greater than an average thickness of said third metal layer by at least 50%; and
wherein at least one element within at least one of said plurality of second transistors has been processed independently of said plurality of third transistors.
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