US 11,990,461 B2
Integrated circuit package for high bandwidth memory
Nam Hoon Kim, San Jose, CA (US); Woon-Seong Kwon, Santa Clara, CA (US); Teckgyu Kang, Saratoga, CA (US); and Yujeong Shim, Cupertino, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Oct. 20, 2022, as Appl. No. 17/970,237.
Application 17/970,237 is a continuation of application No. 17/157,278, filed on Jan. 25, 2021, granted, now 11,488,944, issued on Nov. 1, 2022.
Prior Publication US 2023/0042856 A1, Feb. 9, 2023
Int. Cl. H01L 25/18 (2023.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit package comprising:
a multilayer substrate including a top surface layer and at least one lower layer separated from the top surface layer by a dielectric, the multilayer substrate configured to interface one or more high-bandwidth memory stacks with a logic die, wherein an upper surface of the one or more high-bandwidth memory stacks is configured to receive the multilayer substrate; and
a plurality of printed traces formed in the top surface layer and the at least one lower layer of the multilayer substrate, wherein the plurality of printed traces are configured to provide an interface between the logic die and the one or more high-bandwidth memory stacks.