US 11,990,446 B2
Semiconductor assemblies with redistribution structures for die stack signal routing
Owen R. Fay, Meridian, ID (US); Madison E. Wale, Boise, ID (US); James L. Voelz, Boise, ID (US); Dylan W. Southern, Meridian, ID (US); and Dustin L. Holloway, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 6, 2023, as Appl. No. 18/094,320.
Application 18/094,320 is a continuation of application No. 17/100,610, filed on Nov. 20, 2020, granted, now 11,552,045.
Claims priority of provisional application 63/066,436, filed on Aug. 17, 2020.
Prior Publication US 2023/0145473 A1, May 11, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/82 (2013.01) [H01L 24/20 (2013.01); H01L 24/29 (2013.01); H01L 24/45 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 2224/82203 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor assembly, comprising:
a die stack including a plurality of semiconductor dies;
a routing substrate mounted on the die stack, the routing substrate including an upper surface facing away from the die stack;
a redistribution structure formed above the upper surface of the routing substrate;
a plurality of electrical connectors coupling the redistribution structure to at least some of the plurality of semiconductor dies of the die stack; and
a controller die mounted on the routing substrate electrically coupled to the redistribution structure, wherein the plurality of semiconductor dies are electrically coupled to the controller die via the redistribution structure.