US 11,990,437 B2
System and method for forming solder bumps
Eric Peter Lewandowski, White Plains, NY (US); Jae-Woong Nah, Closter, NJ (US); Jeng-Bang Yau, Yorktown Heights, NY (US); and Peter Jerome Sorce, Poughkeepsie, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 11, 2020, as Appl. No. 16/990,499.
Application 16/990,499 is a division of application No. 16/523,620, filed on Jul. 26, 2019, granted, now 10,879,202.
Prior Publication US 2021/0028138 A1, Jan. 28, 2021
Int. Cl. G06N 5/04 (2023.01); G06F 7/38 (2006.01); G06N 10/00 (2022.01); G06N 10/20 (2022.01); G11C 11/44 (2006.01); H01L 23/00 (2006.01); H10N 60/01 (2023.01); H10N 60/80 (2023.01); H01L 21/60 (2006.01)
CPC H01L 24/11 (2013.01) [G06F 7/381 (2013.01); G06N 10/00 (2019.01); G06N 10/20 (2022.01); G11C 11/44 (2013.01); H01L 24/12 (2013.01); H01L 24/16 (2013.01); H10N 60/0912 (2023.02); H10N 60/805 (2023.02); H01L 2021/60022 (2013.01); H01L 2021/60045 (2013.01); H01L 2021/60067 (2013.01); H01L 2224/11622 (2013.01); H01L 2224/16227 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A superconducting quantum processor, comprising:
a superconducting chip comprising a qubit; and
an interposer connected to the superconducting chip by a plurality of solder interconnections located between the interposer and superconducting chip, the interposer defining a hole therethrough aligned with the qubit on the superconducting chip,
wherein the plurality of solder interconnections forms a wall around the qubit.