US 11,990,425 B2
Stress relief in semiconductor wafers
Hojin Kim, Albany, NY (US); Stephen Mancini, East Greenbush, NY (US); and Soo Doo Chae, Cohoes, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Aug. 18, 2021, as Appl. No. 17/405,265.
Claims priority of provisional application 63/085,554, filed on Sep. 30, 2020.
Prior Publication US 2022/0102289 A1, Mar. 31, 2022
Int. Cl. H01L 21/762 (2006.01); H01L 21/311 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 22/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a plurality of semiconductor devices in a semiconductor wafer, the method comprising:
bowing the semiconductor wafer comprising a substrate by covering the substrate with a strained layer;
forming trenches through the strained layer into the substrate at locations in scribe lines of the semiconductor wafer, respective bottoms of the trenches being located in the substrate below the strained layer, the scribe lines identifying areas between adjacent dies on the semiconductor wafer; and
reducing the bowing of the semiconductor wafer by filling the trenches with a stress-compensation material.