US 11,990,418 B2
Chip package structure with buffer structure and method for forming the same
Chin-Hua Wang, New Taipei (TW); Po-Chen Lai, Hsinchu County (TW); Ping-Tai Chen, Taipei (TW); Che-Chia Yang, Taipei (TW); Yu-Sheng Lin, Chupei (TW); Po-Yao Lin, Hsinchu County (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 27, 2021, as Appl. No. 17/459,266.
Prior Publication US 2023/0061932 A1, Mar. 2, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/48 (2006.01); H01L 21/60 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5384 (2013.01) [H01L 21/486 (2013.01); H01L 21/60 (2021.08); H01L 21/76802 (2013.01); H01L 24/80 (2013.01); H01L 25/0655 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a chip package structure, comprising:
removing a first portion of a substrate to form a first recess in the substrate;
forming a buffer structure in the first recess, wherein a first Young's modulus of the buffer structure is less than a second Young's modulus of the substrate;
forming a first wiring structure over the buffer structure and the substrate, wherein the first wiring structure comprises a first dielectric structure and a first wiring layer in the first dielectric structure; and
bonding a chip package to the first wiring structure, wherein the chip package has an interposer substrate and a chip structure over the interposer substrate, and a first corner of the interposer substrate and a second corner of the chip structure overlap the buffer structure in a top view of the chip package and the buffer structure.