US 11,990,412 B2
Buried power rails located in a base layer including first, second, and third etch stop layers
Ruilong Xie, Niskayuna, NY (US); Stuart Sieg, Albany, NY (US); Somnath Ghosh, Clifton Park, NY (US); Kisik Choi, Watervliet, NY (US); Rishikesh Krishnan, Cohoes, NY (US); and Alexander Reznicek, Troy, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Sep. 29, 2021, as Appl. No. 17/488,389.
Prior Publication US 2023/0100113 A1, Mar. 30, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 23/522 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 21/31116 (2013.01); H01L 21/76816 (2013.01); H01L 21/76829 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 21/823871 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01)] 6 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a frontside device above a base layer, having a channel and source/drain structures;
a buried power rail in the base layer, underneath the frontside device; and
an electrical contact that makes an electrical connection between the buried power rail and the frontside device,
wherein the base layer includes:
a first etch stop layer, which the buried power rail penetrates;
a first semiconductor layer between the first etch stop layer and the frontside device;
a second etch stop layer, between the first semiconductor layer and the frontside device;
a second semiconductor layer between the second etch stop layer and the frontside device; and
a third etch stop layer between the second semiconductor layer and the frontside device.
 
4. An integrated chip, comprising:
a plurality of frontside devices above a base layer, each having a channel and source/drain structures, and having an inter-device distance between an adjacent pair of frontside devices of the plurality of frontside devices;
a buried power rail in the base layer, underneath the pair of frontside devices, having a width that is greater than the inter-device distance; and
an electrical contact that makes an electrical connection between the buried power rail and one of the pair of frontside devices,
wherein the base layer includes:
a first etch stop laver, which the buried power rail penetrates;
a first semiconductor layer between the first etch stop layer and the one of the pair of frontside devices;
a second etch stop layer, between the first semiconductor layer and the one of the pair of frontside devices;
a second semiconductor layer between the second etch stop layer and the one of the pair of frontside devices; and
a third etch stop layer between the second semiconductor layer and the one of the pair of frontside devices.