US 11,990,405 B2
Semiconductor arrangement and method for producing a semiconductor arrangement
Michael Stadler, Munich (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Mar. 25, 2022, as Appl. No. 17/704,672.
Application 17/704,672 is a division of application No. 16/794,922, filed on Feb. 19, 2020, granted, now 11,430,731.
Claims priority of application No. 102019104334.4 (DE), filed on Feb. 20, 2019.
Prior Publication US 2022/0216139 A1, Jul. 7, 2022
Int. Cl. H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/528 (2013.01) [H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01); H01L 2224/04026 (2013.01); H01L 2224/0807 (2013.01); H01L 2224/32145 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method for producing a semiconductor arrangement, the method comprising:
applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer; and
fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material,
wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer,
wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.