US 11,990,403 B2
Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication and structures resulting therefrom
Kevin L. Lin, Beaverton, OR (US); Richard E. Schenker, Portland, OR (US); Jeffery D. Bielefeld, Forest Grove, OR (US); Rami Hourani, Portland, OR (US); and Manish Chandhok, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 30, 2021, as Appl. No. 17/218,080.
Application 17/218,080 is a division of application No. 16/096,272, granted, now 11,011,463, previously published as PCT/US2016/040788, filed on Jul. 1, 2016.
Prior Publication US 2021/0225698 A1, Jul. 22, 2021
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/528 (2013.01) [H01L 21/76807 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76897 (2013.01); H01L 23/5226 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a plurality of alternating first and second conductive line types disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate, the first conductive line type having a different composition than the second conductive line type;
a first hardmask layer disposed over the first conductive line types but not over the second conductive line types, wherein the first hardmask layer is vertically separated from the first conductive line types by a dielectric cap layer; and
a second hardmask layer disposed over the second conductive line types but not over the first conductive line types, wherein the second hardmask layer is directly on the second conductive line types, and wherein the first and second hardmask layers differ in composition.