	US 11,990,401 B2
	Back-end-of-line passive device structure
Tsung-Chieh Hsiao, Changhua County (TW); Hsiang-Ku Shen, Hsinchu (TW); Yuan-Yang Hsiao, Hsinchu (TW); Chen-Chiu Huang, Hsinchu (TW); and Dian-Hau Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 27, 2022, as Appl. No. 17/586,287.
Claims priority of provisional application 63/285,820, filed on Dec. 3, 2021.
Prior Publication US 2023/0178472 A1, Jun. 8, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 49/02 (2006.01)

CPC H01L 23/5223 (2013.01) [H01L 28/75 (2013.01); H01L 28/86 (2013.01); H01L 28/90 (2013.01)]

20 Claims

1. A device structure, comprising:

a passivation layer;

a first conductor plate layer disposed on the passivation layer;

a first dummy pad spaced apart from the first conductor plate layer by a spacing;

a second conductor plate layer disposed over the first conductor plate layer;

a third conductor plate layer disposed over the second conductor plate layer;

a second dummy pad spaced apart from the third conductor plate layer by the spacing;

a fourth conductor plate layer disposed over the third conductor plate layer; and

a third dummy pad spaced apart from the fourth conductor plate layer by the spacing,

wherein the second conductor plate layer encloses the first conductor plate layer,

wherein the fourth conductor plate layer encloses the third conductor plate layer.

12. A device structure, comprising:

a passivation layer;

a first conductor plate layer disposed on the passivation layer;

a first dummy pad spaced apart from the first conductor plate layer by a spacing;

a second conductor plate layer disposed over the first conductor plate layer;

a third conductor plate layer disposed over the second conductor plate layer;

a second dummy pad spaced apart from the third conductor plate layer by the spacing;

a fourth conductor plate layer disposed over the third conductor plate layer; and

a third dummy pad spaced apart from the fourth conductor plate layer by the spacing,

wherein, along a direction, the first conductor plate layer comprises a first width, the second conductor plate layer comprises a second width, the third conductor plate layer comprises a third width, and the fourth conductor plate layer comprises a fourth width,

wherein the second width is greater than the first width and the fourth width is greater than the third width.

17. A device structure, comprising:

a passivation layer;

a first conductor plate layer disposed on the passivation layer;

a first dummy pad spaced apart from the first conductor plate layer by a spacing;

a second conductor plate layer disposed over the first conductor plate layer;

a third conductor plate layer disposed over the second conductor plate layer;

a second dummy pad spaced apart from the third conductor plate layer by the spacing;

a fourth conductor plate layer disposed over the third conductor plate layer; and

a third dummy pad spaced apart from the fourth conductor plate layer by the spacing,

wherein an area of the second conductor plate layer is greater an area of the first conductor plate layer,

wherein an area of the fourth conductor plate layer is greater than the third conductor plate layer.