US 11,990,400 B2
Capping layer overlying dielectric structure to increase reliability
Ting-Ya Lo, Hsin-Chu (TW); Chi-Lin Teng, Taichung (TW); Hai-Ching Chen, Hsinchu (TW); Hsin-Yen Huang, New Taipei (TW); Shau-Lin Shue, Hsinchu (TW); Shao-Kuan Lee, Kaohsiung (TW); and Cheng-Chin Lee, Taipei (TW)
Assigned to Taiwan SemiconductorManufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 1, 2022, as Appl. No. 17/829,590.
Application 17/829,590 is a division of application No. 16/885,378, filed on May 28, 2020, granted, now 11,355,430.
Claims priority of provisional application 62/949,560, filed on Dec. 18, 2019.
Prior Publication US 2022/0293512 A1, Sep. 15, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/5222 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming an integrated chip, the method comprising:
forming a first conductive wire and a second conductive wire over a substrate;
forming a dielectric structure laterally between the first conductive wire and the second conductive wire, wherein the dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer, wherein a top surface of the first dielectric liner is aligned with a top surface of the dielectric layer; and
forming a dielectric capping layer along an upper surface of the dielectric structure, wherein sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.