US 11,990,394 B2
Semiconductor package and a method for manufacturing of a semiconductor package
Kim Ng, Nijmegen (NL); On Lok Chau, Nijmegen (NL); Wai Keung Ho, Nijmegen (NL); and Raymond Wong, Nijmegen (NL)
Assigned to Nexperia B.V., Nijmegen (NL)
Filed by NEXPERIA B.V., Nijmegen (NL)
Filed on Sep. 15, 2021, as Appl. No. 17/475,612.
Claims priority of application No. 20196426 (EP), filed on Sep. 16, 2020.
Prior Publication US 2022/0084919 A1, Mar. 17, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/49582 (2013.01) [H01L 21/4821 (2013.01); H01L 23/31 (2013.01); H01L 23/53242 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a lead frame having a lead frame surface;
an Ag plated surface positioned on the lead frame;
an adhesion promotion layer positioned on a top of the Ag plated surface; and
a mold body covering a top of the lead frame;
wherein the Ag plated surface covers a significant part of an interconnection area of the lead frame surface, and wherein the Ag plated surface does not substantially exceed an area of the mold body so that a portion of the lead frame surface extending beyond the area of the mold body is free from Ag plating.