US 11,990,345 B2
Patterning method and semiconductor structure
Qiang Wan, Hefei (CN); Jun Xia, Hefei (CN); Kangshu Zhan, Hefei (CN); Sen Li, Hefei (CN); Tao Liu, Hefei (CN); and Penghui Xu, Hefei (CN)
Assigned to Changxin Memory Technologies, Inc., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 14, 2022, as Appl. No. 17/647,994.
Application 17/647,994 is a continuation of application No. PCT/CN2021/112608, filed on Aug. 13, 2021.
Claims priority of application No. 202110338758.6 (CN), filed on Mar. 30, 2021.
Prior Publication US 2022/0319857 A1, Oct. 6, 2022
Int. Cl. H01L 21/308 (2006.01); H01L 21/033 (2006.01)
CPC H01L 21/3086 (2013.01) [H01L 21/0337 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A patterning method, comprising:
providing a substrate, wherein the substrate comprises adjacent storage regions and peripheral circuit regions;
forming, on the substrate, a pattern transfer layer, the pattern transfer layer having a plurality of first hard masks, wherein the first hard masks extend along a first direction and are spaced apart from each other; and forming a barrier layer on the pattern transfer layer;
forming, on the barrier layer, a plurality of second hard masks, the plurality of second hard masks extending along a second direction, wherein the second hard masks are spaced apart from each other; and
the second hard masks are located in the storage regions and second hard masks close to the peripheral circuit regions have structural defects;
forming a first buffer layer on the barrier layer, and filling the second hard masks that have the structural defects with the first buffer layer, wherein an orthographic projection of the first buffer layer overlaps the peripheral circuit regions and a part of each of the storage regions; and
patterning the barrier layer and the pattern transfer layer by using the first buffer layer and second hard masks not filled with the first buffer layer as a mask.