US 11,990,341 B2
Cut metal gate processes
Shu-Uei Jang, Hsinchu (TW); Ya-Yi Tsai, Hsinchu (TW); Ryan Chia-Jen Chen, Hsinchu (TW); An Chyi Wei, Hsinchu (TW); and Shu-Yuan Ku, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 9, 2022, as Appl. No. 17/818,600.
Application 17/818,600 is a continuation of application No. 16/927,031, filed on Jul. 13, 2020, granted, now 11,508,582.
Application 16/927,031 is a continuation of application No. 16/182,772, filed on Nov. 7, 2018, granted, now 10,714,347, issued on Jul. 14, 2020.
Claims priority of provisional application 62/751,067, filed on Oct. 26, 2018.
Prior Publication US 2022/0384616 A1, Dec. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/28123 (2013.01) [H01L 21/02164 (2013.01); H01L 21/32135 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a gate stack extending over a semiconductor region;
forming gate spacers, wherein the gate spacers are on first sidewalls of the gate stack;
etching the gate stack to form a trench extending into the gate stack;
removing a dielectric layer from the trench to reveal second sidewalls of the gate stack, wherein the second sidewalls face the trench; and
filling the trench with a dielectric material to form a dielectric isolation region, wherein the dielectric isolation region contacts the second sidewalls of the gate stack.