US 11,990,336 B2
Silicon epitaxial wafer production method and silicon epitaxial wafer
Masayuki Ishibashi, Tokyo (JP); Midori Yoshida, Tokyo (JP); and Daisuke Maruoka, Tokyo (JP)
Assigned to SUMCO CORPORATION, Tokyo (JP)
Appl. No. 17/296,281
Filed by SUMCO CORPORATION, Tokyo (JP)
PCT Filed Aug. 5, 2019, PCT No. PCT/JP2019/030722
§ 371(c)(1), (2) Date May 24, 2021,
PCT Pub. No. WO2020/136973, PCT Pub. Date Jul. 2, 2020.
Claims priority of application No. 2018-245109 (JP), filed on Dec. 27, 2018.
Prior Publication US 2022/0020585 A1, Jan. 20, 2022
Int. Cl. H01L 21/02 (2006.01); C30B 25/10 (2006.01); H01L 21/306 (2006.01)
CPC H01L 21/02532 (2013.01) [C30B 25/10 (2013.01); H01L 21/02433 (2013.01); H01L 21/0262 (2013.01); H01L 21/30625 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A method for producing a silicon epitaxial wafer in which an epitaxial layer is grown in a vapor phase on a principal plane of a silicon single crystal wafer, the principal plane being a plane or a plane having an off-angle of less than 1 degree from the plane, the method comprising:
setting a temperature of the silicon single crystal wafer to 1100° C. to 1135° C.; and
growing the epitaxial layer in the vapor phase at a growth rate of 2.0 μm/min to 3.0 μm/min so that a number of microscopic step defects having a height over 3 nm on a surface of the epitaxial layer when observed using a differential interference contrast method is 1.5/300 mm wafer or less.