US 11,990,264 B2
Chip inductor and method for manufacturing the same
Takuma Shimoichi, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Jul. 21, 2021, as Appl. No. 17/381,633.
Application 17/381,633 is a continuation of application No. 15/940,002, filed on Mar. 29, 2018, granted, now 11,094,447.
Claims priority of application No. 2017-068593 (JP), filed on Mar. 30, 2017; application No. 2017-070627 (JP), filed on Mar. 31, 2017; and application No. 2018-015350 (JP), filed on Jan. 31, 2018.
Prior Publication US 2021/0350970 A1, Nov. 11, 2021
Int. Cl. H01F 27/28 (2006.01); H01F 17/00 (2006.01); H01F 27/29 (2006.01); H01F 27/32 (2006.01); H01F 41/04 (2006.01); H01F 41/10 (2006.01); H01F 41/12 (2006.01)
CPC H01F 27/28 (2013.01) [H01F 17/0013 (2013.01); H01F 27/29 (2013.01); H01F 27/292 (2013.01); H01F 27/323 (2013.01); H01F 41/04 (2013.01); H01F 41/041 (2013.01); H01F 41/10 (2013.01); H01F 41/122 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A chip component comprising:
a sealing body having mounting surface and a non-mounting surface that are formed in oblong shapes, the sealing body further having a first connecting surface and a second connecting surface connected to short sides of the mounting surface, and a third connecting surface and a fourth connecting surface connected to long sides of the mounting surface;
an inductor that is sealed inside the sealing body; and
a capacitor that is sealed inside the sealing body together with the inductor, wherein
the sealing body has a laminated structure in which a plurality of insulating layers are laminated from the third connecting surface to the fourth connecting surface,
the capacitor includes a first conductor and a second conductor that face each other across a dielectric portion in an orthogonal direction to a lamination direction of the plurality of insulating layers, and
the first conductor and the second conductor are formed in a plate shape extending along the lamination direction.