US 11,990,203 B2
Neural processing unit capable of testing component therein during runtime
Lok Won Kim, Seongnam-si (KR); and Jeong Kyun Yim, Anyang-si (KR)
Assigned to DEEPX CO., LTD., Seongnam-si (KR)
Filed by DEEPX CO., LTD., Seongnam-si (KR)
Filed on Jun. 26, 2022, as Appl. No. 17/849,667.
Claims priority of application No. 10-2022-0054878 (KR), filed on May 3, 2022.
Prior Publication US 2023/0359180 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/26 (2006.01); G05B 19/418 (2006.01); G11C 29/00 (2006.01); G11C 29/10 (2006.01)
CPC G11C 29/78 (2013.01) [G05B 19/41875 (2013.01); G06F 11/26 (2013.01); G11C 29/10 (2013.01); G05B 2219/32368 (2013.01); G05B 2219/45031 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A neural processing unit (NPU) for testing a component of the NPU during runtime, the NPU comprising:
a plurality of functional components, each of the plurality of functional components including an electronic circuit;
at least one wrapper connected to at least one functional component of the plurality of functional components;
a field programmable gate array (FPGA); and
an in-system component tester (ICT) configured to:
select one of the at least one functional component, in an idle state, as a component under test (CUT), prepare or start a test, via the at least one wrapper, of the selected functional component,
stop the test, based on a detection of a collision due to an access to the selected functional component, and
complete the test, when no collision is detected,
wherein when the selected functional component is determined to be defective during the test, the FPGA is configured to imitate a normal function of the selected functional component.