US 11,990,200 B2
Bit retiring to mitigate bit errors
Scott E. Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 20, 2022, as Appl. No. 17/580,329.
Claims priority of provisional application 63/142,781, filed on Jan. 28, 2021.
Prior Publication US 2022/0238175 A1, Jul. 28, 2022
Int. Cl. G11C 29/44 (2006.01); G11C 29/12 (2006.01); G11C 29/18 (2006.01); G11C 29/42 (2006.01)
CPC G11C 29/4401 (2013.01) [G11C 29/1201 (2013.01); G11C 29/18 (2013.01); G11C 29/42 (2013.01); G11C 2029/1806 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A method, comprising:
retrieving a set of bits from a first row of an address space of a memory array, the address space addressable by a host device;
determining that the set of bits includes one or more errors;
remapping at least a portion of the first row from a first row index to a second row index based at least in part on determining that the set of bits includes the one or more errors, wherein the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device; and
remapping at least a portion of the second row from the second row index to the first row index based at least in part on remapping at least the portion of the first row to the second row index.