US 11,990,199 B2
Centralized error correction circuit
Taeksang Song, San Jose, CA (US); Saira Samar Malik, Lafayette, IN (US); Hyunyoo Lee, Boise, ID (US); Chinnakrishnan Ballapuram, San Jose, CA (US); and Kang-Yong Kim, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 5, 2022, as Appl. No. 17/647,152.
Claims priority of provisional application 63/140,096, filed on Jan. 21, 2021.
Prior Publication US 2022/0230698 A1, Jul. 21, 2022
Int. Cl. G11C 29/42 (2006.01); G11C 29/12 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/1201 (2013.01); G11C 29/4401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a non-volatile memory disposed on a first die;
a volatile memory disposed on a second die different than the first die and configured to operate as a cache for the non-volatile memory, the volatile memory comprising a plurality of banks; and
an interface controller disposed on a third die different than the first die and different than the second die and coupled with the non-volatile memory and the volatile memory, the interface controller comprising an error correction code (ECC) circuit, comprising an ECC decoder, that is coupled with the non-volatile memory and the volatile memory, the ECC decoder configured to:
perform a first error detection operation on a first codeword, received from the non-volatile memory, that comprises first data for transfer from the non-volatile memory to the volatile memory; and
perform a second error detection operation on a second codeword, received from the volatile memory, that comprises second data for transfer from the volatile memory to the non-volatile memory.