US 11,990,198 B2
Memory system and operation method of memory system
Chul Moon Jung, Gyeonggi-do (KR); Uk Song Kang, Gyeonggi-do (KR); and Woongrae Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 13, 2021, as Appl. No. 17/549,564.
Claims priority of provisional application 63/129,074, filed on Dec. 22, 2020.
Claims priority of application No. 10-2021-0163743 (KR), filed on Nov. 24, 2021.
Prior Publication US 2022/0199186 A1, Jun. 23, 2022
Int. Cl. G11C 29/42 (2006.01); G11C 17/16 (2006.01); G11C 29/18 (2006.01); G11C 29/44 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 17/16 (2013.01); G11C 29/18 (2013.01); G11C 29/4401 (2013.01); G11C 2029/1202 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A memory system, comprising:
an address scrambler suitable for scrambling an address based on a scrambling pattern to generate a scrambled address;
a memory core including a plurality of memory cells and suitable for storing data in memory cells designated by the scrambled address;
a scramble control circuit suitable for changing the scrambling pattern of the address scrambler in response to satisfaction of an attack condition;
a row hammer attack pattern detecting circuit suitable for detecting a row hammer attack pattern with respect to the memory core; and
an error correction circuit suitable for detecting and correcting an error in data read from the memory core,
wherein the scramble control circuit is further suitable for determining the attack condition as satisfied when the row hammer attack pattern detecting circuit detects the row hammer attack pattern for one row of memory cells within the memory core and the error correction circuit detects an error equal to or greater than a threshold value in neighboring rows of the row.