CPC G11C 29/36 (2013.01) [G11C 14/0063 (2013.01); G11C 5/148 (2013.01); G11C 2029/3602 (2013.01)] | 20 Claims |
1. A circuit comprising:
a non-volatile storage array comprising a plurality of non-volatile cells;
control logic coupled to the non-volatile storage array;
a computing register coupled to the non-volatile storage array and to the control logic, the computing register comprising a plurality of latches, each of the plurality of latches of the computing register is coupled to a respective one of the plurality of non-volatile cells by a data bus, each latch comprising:
a first latch portion having an output; and
a second latch portion having a first input port coupled to the output of the first latch portion and a second input port coupled to the respective non-volatile cell, the second latch portion includes an inverter having:
first and second switches connected in series; and
third and fourth switches connected in series; and
the first and second switches are arranged in parallel with the third and fourth switches.
|