US 11,990,196 B2
Computing register with non-volatile-logic data storage
Adolf Baumann, Haag (DE); and Mark Jung, Freising (DE)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Mar. 7, 2023, as Appl. No. 18/179,434.
Application 18/179,434 is a continuation of application No. 17/101,132, filed on Nov. 23, 2020, granted, now 11,600,351.
Application 17/101,132 is a continuation of application No. 14/555,552, filed on Nov. 26, 2014, granted, now 10,847,242, issued on Nov. 24, 2020.
Claims priority of provisional application 62/028,119, filed on Jul. 23, 2014.
Prior Publication US 2023/0207036 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/36 (2006.01); G11C 14/00 (2006.01); G11C 5/14 (2006.01)
CPC G11C 29/36 (2013.01) [G11C 14/0063 (2013.01); G11C 5/148 (2013.01); G11C 2029/3602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a non-volatile storage array comprising a plurality of non-volatile cells;
control logic coupled to the non-volatile storage array;
a computing register coupled to the non-volatile storage array and to the control logic, the computing register comprising a plurality of latches, each of the plurality of latches of the computing register is coupled to a respective one of the plurality of non-volatile cells by a data bus, each latch comprising:
a first latch portion having an output; and
a second latch portion having a first input port coupled to the output of the first latch portion and a second input port coupled to the respective non-volatile cell, the second latch portion includes an inverter having:
first and second switches connected in series; and
third and fourth switches connected in series; and
the first and second switches are arranged in parallel with the third and fourth switches.