US 11,990,195 B2
Semiconductor device with selective command delay and associated methods and systems
Boon Hor Lam, Boise, ID (US); Shawn M. Hilde, Meridian, ID (US); Karl L. Major, Boise, ID (US); and Garrett Harwell, Meridian, ID (US)
Filed by Lodestar Licensing Group LLC
Filed on Sep. 23, 2022, as Appl. No. 17/935,057.
Application 17/935,057 is a division of application No. 16/839,371, filed on Apr. 3, 2020, granted, now 11,468,960.
Claims priority of provisional application 62/955,701, filed on Dec. 31, 2019.
Prior Publication US 2023/0014661 A1, Jan. 19, 2023
Int. Cl. G11C 29/12 (2006.01); G11C 7/10 (2006.01); G11C 11/406 (2006.01); G11C 29/14 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/12015 (2013.01) [G11C 7/1048 (2013.01); G11C 11/40615 (2013.01); G11C 29/14 (2013.01); G11C 29/44 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method, comprising:
setting a mode register of a memory device to indicate a mode, in which one or more commands are associated with a delay;
operating the memory device in the mode, in which the one or more commands directed to the memory device are associated with the delay;
determining that a set of signals received from a host device at the memory device includes at least one of the commands; and
executing the command at the memory device after the delay based at least in part on operating the memory device in the mode, in which the one or more commands are associated with the delay.